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tcs3404, TCS3414 digital color sensors taos137a ? april 2011 1 the lumenology company copyright 2011, taos inc. www.taosinc.com features programmable interrupt function with user-defined upper and lower threshold settings internal filter eliminates signal fluctuation due to ac lighting flicker ? no external capacitor required in-package trim provides an easy and accurate means to achieve system-to-system repeatability 16-bit digital output with i 2 c at 400 khz programmable analog gain and integration time supporting 1,000,000-to-1 dynamic range sync input synchronizes integration cycle to modulated light sources (e.g. pwm) operating temperature range ?40 c to 85 c (cs package) ?30 c to 70 c (fn package) operating voltage of 2.7 v to 3.6 v available in both an fn and a cs package. the cs package is the industry?s smallest digital rgb color sensor applications provides method to derive chromaticity coordinates to manage display backlighting (i.e. rgb led, ccfl, etc.) provides means to derive color temperature to white-color balance displays under various lighting conditions end products and market segments hdtvs tablets, laptops, monitors medical instrumentation consumer toys industrial/commercial lighting industrial process control description the tcs3404 and TCS3414 digital color light sensors are designed to accurately derive the color chromaticity and illuminance (intensity) of ambient light and provide a digital output with 16-bits of resolution. the devices include an 8 2 array of filtered photodiodes, analog-to-digital converters, and control functions on a single monolithic cmos integrated circuit. of the 16 photodiodes, 4 have red filters, 4 have green filters, 4 have blue filters, and 4 have no filter (clear). with the advanced patent pending in-package trim capability, device-to-device and system-to-system tolerance can be minimized allowing very precise repeatability to be attained. texas advanced optoelectronic solutions inc. 1001 klein road suite 300 plano, tx 75074 (972) 673-0759 package cs 6-lead chipscale (top view) scl a1 sync a2 gnd a3 b1 sda b2 vdd b3 int package fn dual flat no-lead (top view) 6 gnd 5 v dd 4 int scl 1 sync 2 sda 3 package drawings are not to scale ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 2 copyright 2011, taos inc. the lumenology company www.taosinc.com a synchronization input (sync) provides precise external control of sensor integration allowing the internal conversion cycles to be synchronized to a pulsed light source. furthermore, the synchronization feature supports the following advanced modes of operation to maximize flexibility across a broad range of hardware systems: (1) sync for one internal-time cycle, and (2) accumulate for specified number of pulses. the device also supports free-running and serial-bus-controlled integration modes if precise coupling between the sensor and light source is not required. four parallel analog-to-digital converters (adc) transform the photodiode currents to an smbus (tcs3404) or i 2 c (TCS3414) digital output that, in turn, can be input to a microprocessor. the rgb values can be read in a single read cycle to minimize the number of read command protocols defined in the communication interface. the slave address for this device is 39h (0111001b). a single smb-alert style interrupt (tcs3404) as well as a single traditional level -style interrupt (TCS3414) can be dynamically configured for any one of the four channels including a corresponding high/low threshold setting. the interrupt will remain asserted until the firmware clears the interrupt. the tcs3404/14 devices can help (1) automatically adjust the display brightness of a backlight to extend battery, increase lamp life, and provide optimum viewing in diverse lighting conditions, (2) white-color balance display panel and/or captured images in diverse lighting conditions, and (3) manage rgb led backlighting to maintain color consistency over a long period of time. these devices are also ideal in controlling keyboard illumination in low ambient light conditions. chromaticity coordinates (x,y) can be used to derive color temperature for the purpose of white-color balancing of displays and/or captured images. illuminance, in lux, can be used to approximate the human eye response of ambient light and to manage exposure control in digital cameras. the tcs3404/14 devices are ideal in notebook/tablet pcs, lcd monitors, flat-panel televisions, cell phones, and digital cameras. additional applications include street light control, security lighting, sunlight harvesting, and automotive instrumentation clusters. functional block diagram two-wire serial interface interrupt sda v dd blue channel clear channel command register 4-parallel adc registers int scl green channel red channel integrating a/d converter integrating a/d converter integrating a/d converter integrating a/d converter synchronization sync ir-blocking filter (cs package only) ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 3 the lumenology company copyright 2011, taos inc. www.taosinc.com terminal functions terminal name cs pkg no. fn pkg no. type description gnd a3 6 power supply ground. all voltages are referenced to gnd. int b3 4 o level interrupt ? open drain. scl a1 1 i serial clock input terminal ? clock signal for i 2 c serial data. sda b1 3 i/o serial data i/o terminal ? serial data i/o for i 2 c. sync a2 2 i synchronous input. v dd b2 5 supply voltage. available options device interface i 2 c address package ? leads package designator ordering number tcs3404 smbus ? chipscale?6 cs tcs3404cs tcs3404 smbus ? dual flat no-lead?6 fn tcs3404fn tcs3413 i 2 c 0x29 chipscale?6 cs tcs3413cs tcs3413 i 2 c 0x29 dual flat no-lead?6 fn tcs3413fn TCS3414 ? i 2 c 0x39 chipscale?6 cs TCS3414cs TCS3414 ? i 2 c 0x39 dual flat no-lead?6 fn TCS3414fn tcs3415 i 2 c 0x49 chipscale?6 cs tcs3415cs tcs3415 i 2 c 0x49 dual flat no-lead?6 fn tcs3415fn tcs3416 i 2 c 0x59 chipscale?6 cs tcs3416cs tcs3416 i 2 c 0x59 dual flat no-lead?6 fn tcs3416fn ? recommended device for single-device systems.. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage, v dd (see note 1) 3.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital output voltage range, v o ?0.5 v to 3.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital output current, i o ?1 ma to 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . esd tolerance, human body model 2000 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltages are with respect to gnd. recommended operating conditions min nom max unit supply voltage, v dd 2.7 3 3.6 v operating free-air temperature, t a (cs package) ?40 85 c operating free-air temperature, t a (fn package) ?30 70 c scl, sda input low voltage, v il ?0.5 0.8 v scl, sda input high voltage, v ih 2.1 3.6 v ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 4 copyright 2011, taos inc. the lumenology company www.taosinc.com electrical characteristics, t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit power on (adc inactive) 7.7 10 ma i dd supply current @ v dd = 3.6 v power on (adc active) 8.7 11 ma i dd supply current @ v dd 3.6 v power down 700 1000 a v ol int, sda output low voltage 3 ma sink current 0 0.4 v i leak input leakage current (sda, scl, sync) v ih = v dd, v il = gnd ?5 5 a ac electrical characteristics, v dd = 3.3 v, t a = 25 c (unless otherwise noted) parameter ? test conditions min typ max unit f clock frequency 400 khz (i 2 c) 0 400 khz f (scl) clock frequency 100 khz (smbus) 10 100 khz t (buf) bus free time between start and stop condition 1.3 s t (hdsta) hold time after (repeated) start condition. after this period, the first clock is generated. 0.6 s t (susta) repeated start condition setup time 0.6 s t (susto) stop condition setup time 0.6 s t (hddat) data hold time 0 0.9 s t (sudat) data setup time 100 ns t (low) scl clock low period 1.3 s t (high) scl clock high period 0.6 s t (timeout) detect clock/data low timeout (smbus only) 25 35 ms t f clock/data fall time 300 ns t r clock/data rise time 300 ns c i input pin capacitance 10 pf t low (sync) sync low period (see figure 1) 50 s t high (sync) sync high period (see figure 1) 50 s t f (sync) sync fall time (see figure 1) 50 ns t r (sync) sync rise time (see figure 1) 50 ns ? specified by design and characterization; not production tested. t high (sync) t f (sync) t r (sync) t low (sync) figure 1. timing diagram for sync ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 5 the lumenology company copyright 2011, taos inc. www.taosinc.com optical characteristics, v dd = 3 v, t a = 25 c, gain = 64 , tint = 12ms (unless otherwise noted) (see notes 1 and 2) parameter test red channel green channel blue channel clear channel unit parameter test conditions min typ max min typ max min typ max min typ max unit irradiance p = 470 nm, see note 3 0% 15% 15% 50% 65% 90% 59.0 65.6 72.5 r e responsivity (cs package) p = 524 nm, see note 4 0% 15% 60% 90% 0% 35% 71.2 76.9 82.7 (counts/ w/ cm 2 ) pac k age ) p = 640 nm, see note 5 80% 110% 0% 15% 0% 15% 80.6 90.1 99.5 cm 2 ) irradiance p = 470 nm, see note 3 0% 15% 10% 50% 65% 90% 56.3 62.5 69.1 r e responsivity (fn package) p = 524 nm, see note 4 0% 15% 60% 90% 0% 35% 72.5 78.4 84.3 (counts/ w/ cm 2 ) pac k age ) p = 640 nm, see note 5 80% 110% 0% 15% 0% 15% 94.2 105.3 116.3 cm 2 ) notes: 1. the percentage shown represents the ratio of the respective red, green, or blue channel value to the clear channel valu e. 2. optical measurements are made using small-angle incident radiation from a light-emitting diode (led) optical source. 3. the 470 nm input irradiance is supplied by an i ngan light-emitting diode with the following characteristics: peak wavelength p = 470 nm, spectral halfwidth ? ? = 35 nm, and luminous efficacy = 75 lm/w. 4. the 524 nm input irradiance is supplied by an i ngan light-emitting diode with the following characteristics: peak wavelength p = 524 nm, spectral halfwidth ? ? = 47 nm, and luminous efficacy = 520 lm/w. 5. the 640 nm input irradiance is supplied by a al i ngap light-emitting diode with the following characteristics: peak wavelength p = 640 nm, spectral halfwidth ? ? = 17 nm, and luminous efficacy = 155 lm/w. 6. illuminance responsivity r v is calculated from the irradiance responsivity r e by using the led luminous efficacy values stated in notes 3, 4, and 5 and using 1 lx = 1 lm/m 2 . operating characteristics, v dd = 3 v, t a = 25 c, (unless otherwise noted) (see notes 2, 3, and 4) parameter test conditions min typ max unit 4 3.8 4 4.2 gain scaling, relative to 1 gain setting 16 15.2 16 16.8 gain scaling, relative to 1 gain setting 64 60.8 64 67.2 dark adc count value e e = 0, 64 gain setting, t int = 400 ms 0 3 15 counts maximum digital count value prescale = 1, t int = 400 ms (note 1) 65535 counts f osc oscillator frequency 4.2 4.4 4.6 mhz internal integration time tolerance ?5 5 % temperature coefficient of responsivity (sync mode) 700 nm, ? 40 c t a 85 c 200 ppm/ c notes: 1. at shorter integration times and/or higher prescale settings, the device will reach saturation of the analog section before the digital count reaches the maximum 16-bit value. the worst-case (lowest) analog saturation value can be obtained using the formula: analog saturation = (fosc(min) tint) prescale, where fosc(min) is the minimum oscillator frequency in hz, and tint is the actual integration time (internal, manually-timed, or sync-generated) in seconds. 2. gain is controlled by the gain register (07h) described in the register section. 3. measurements taken when the photodiode field value in the photodiode register (06h) is 00b and when the prescaler field value in the gain register (07h) is 000b. 4. the full scale adc count value is slew-rate limited for short integration times and is limited by the 16-bit counter for long integration times. the nominal transition between the two regions is t int = 65535/5000 = 13.1 ms. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 6 copyright 2011, taos inc. the lumenology company www.taosinc.com parameter measurement information sda scl stop start scl ack t (lowmext) t (lowmext) t (lowsext) scl ack t (lowmext) start condition stop condition p sda t (susto) t (sudat) t (hddat) t (buf) v ih v il scl t (susta) t (high) t (f) t (r) t (hdsta) t (low) v ih v il ps s figure 2. timing diagrams a0a1a2a3a4a5a6 scl start by master sda 19 19 d1d2d3d4d5d6d7 d0 r/w frame 1 slave address byte frame 2 command byte ack by tcs3404/14 stop by master ack by tcs3404/14 figure 3. example timing diagram for send byte format a0a1a2a3a4a5a6 scl start by master sda 19 19 d1d2d3d4d5d6d7 d0 r/w frame 1 slave address byte frame 2 data byte from tcs3404/14 ack by tcs3404/14 stop by master nack by master figure 4. example timing diagram for receive byte format ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 7 the lumenology company copyright 2011, taos inc. www.taosinc.com typical characteristics figure 5 spectral responsivity cs package ? wavelength ? nm 0 400 20 40 60 80 100 500 600 700 800 900 1000 1100 normalized responsivity ? % 300 clear blue green red figure 6 spectral responsivity fn package ? wavelength ? nm 0 400 20 40 60 80 100 500 600 700 800 900 1000 1100 normalized responsivity ? % 300 120 clear red green blue note: spectral responsivity is normalized at 655 nm. note: spectral responsivity is normalized at 850 nm. figure 7 i dd off vs. free-air temperature (power down) t a ? free-air temperature ? c i dd ? a 600 650 700 750 800 850 900 950 0 25 50 75 100 3.6 v 2.7 v 3.0 v 3.3 v figure 8 i dd ? ma 0 25 50 75 100 i dd on vs. free-air temperature (power on ? adc inactive) t a ? free-air temperature ? c 2.7 v 3.0 v 7.0 7.5 8.0 8.5 9.0 9.5 3.6 v 3.3 v note: when the device is powered on and the adc is active, i dd is approximately 1 ma higher. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 8 copyright 2011, taos inc. the lumenology company www.taosinc.com typical characteristics figure 9 98 99 100 101 102 103 104 105 106 97 t int normalized ? % 0 25 50 75 100 normalized integration time vs. free-air temperature t a ? free-air temperature ? c externally timed integration internally timed integration figure 10 normalized responsivity vs. angular displacement ? fn package ? angular displacement ? n orma li ze d r espons i v it y 0 0.2 0.4 0.6 0.8 1.0 ?90 ?60 ?30 0 30 60 90 optical axis figure 11 normalized responsivity vs. angular displacement?cs package ? angular displacement ? normalized responsivity 0 0.2 0.4 0.6 0.8 1 ?90 ?60 ?30 0 30 60 90 optical axis figure 12 normalized responsivity vs. angular displacement?cs package ? angular displacement ? normalized responsivity 0 0.2 0.4 0.6 0.8 1 ?90 ?60 ?30 0 30 60 90 optical axis ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 9 the lumenology company copyright 2011, taos inc. www.taosinc.com principles of operation analog-to-digital converter the tcs3404/14 contains four integrating analog-to-digital converters (adc) that integrate the currents from the four photodiodes (channel 1 through channel 4). integration of all four channels occurs simultaneously, and upon completion of the conversion cycle the conversion results are transferred to the channel data registers, respectively. the transfers are double-buffered to ensure that invalid data is not read during the transfer. after the transfer, the device automatically begins the next integration cycle. there are two ways to control the integration cycles: internally timed and externally timed. internally-timed integration cycles can either be continuous back-to-back conversions or can be externally triggered as a single event using the sync pin. externally-timed integrations can be controlled by setting and clearing a register bit (i.e. adc_en in control register) using the serial interface, or by 1 or more pulses input to the sync pin. integration options are configured through the timing register (see the timing register section for more information). digital interface interface and control of the tcs3404/14 is accomplished through a two-wire serial interface to a set of registers that provide access to device control functions and output data. the serial interface is compatible with system management bus (smbus) versions 1.1 and 2.0, and i 2 c bus fast-mode. the tcs3404/14 device supports a single slave address outlined in table 1. additional devices shown in the available options table on page 3 support additional i 2 c slave addresses for systems requiring more than one device. table 1. slave address slave address smb alert address 0111001 0001100 note: the slave and smb alert addresses are 7 bits. please note the smbus and i 2 c protocols on the following pages. a read/write bit should be appended to the slave address by the master device to communicate properly with the device. interrupt although the adc channel data registers can be read at any time to obtain the most recent conversion value, in some applications, periodic polling of the device may not be desirable. for these types of applications, the device supports a variety of interrupt options allowing the user to configure the device to signal when a change in light intensity has occurred. high and low threshold registers allow a range of light levels to be defined, outside of which the device generates an interrupt. a persistence setting allows the user to specify a time duration that the measured value must remain outside of the defined range before generating an interrupt. the interrupt function can be assigned to any one of the four adc color channels. see interrupt control register for more information on configuring the interrupt functions. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 10 copyright 2011, taos inc. the lumenology company www.taosinc.com smbus and i 2 c protocols each send and write protocol is, essentially, a series of bytes. a byte sent to the tcs3404/14 with the most significant bit (msb) equal to 1 will be interpreted as a command byte. the lower four bits of the command byte form the register select address (see table 1), which is used to select the destination for the subsequent byte(s) received. the tcs3404/14 responds to any receive byte requests with the contents of the register specified by the stored register select address. the tcs3404/14 implements the following protocols of the smb 2.0 specification: send byte protocol receive byte protocol write byte protocol write word protocol read word protocol block write protocol block read protocol the tcs3404/14 implements the following protocols of the i 2 c specification: i 2 c write protocol i 2 c read (combined format) protocol when an smbus block write or block read is initiated (see description of command register), the byte following the command byte is ignored but is a requirement of the smbus specification. this field contains the byte count (i.e. the number of bytes to be transferred). the tcs3404 (smbus) device ignores this field and extracts this information by counting the actual number of bytes transferred before the stop condition is detected. when an i 2 c write or i 2 c read (combined format) is initiated, the byte count is also ignored but follows the smbus protocol specification. data bytes continue to be transferred from the TCS3414 (i 2 c) device to master until a nack is sent by the master. the data formats supported by the tcs3404 and TCS3414 devices are: master transmitter transmits to slave receiver (smbus and i 2 c): ? the transfer direction in this case is not changed. master reads slave immediately after the first byte (smbus only): ? at the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. combined format (smbus and i 2 c): ? during a change of direction within a transfer, the master repeats both a start condition and the slave address but with the r/w bit reversed. in this case, the master receiver terminates the transfer by generating a nack on the last byte of the transfer and a stop condition. for a complete description of smbus protocols, please review the smbus specification at http://www.smbus.org/specs. for a complete description of the i 2 c protocol, please review the nxp i 2 c design specification at http://www.i2c?bus.org/references/. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 11 the lumenology company copyright 2011, taos inc. www.taosinc.com wr 7 data byte slave address s 1 ap a 8 11 11 xx a acknowledge (this bit position may be 0 for an ack or 1 for a nack) p stop condition rd read (bit value of 1) s start condition sr repeated start condition wr write (bit value of 0) x shown under a field indicates that that field is required to have a value of x ... continuation of protocol master-to-slave slave-to-master figure 13. smbus and i 2 c packet protocol element key wr 7 data byte slave address s 1 ap a 8 11 11 figure 14. smbus send byte protocol rd 7 data byte slave address s 1 ap a 8 11 11 1 figure 15. smbus receive byte protocol wr 7 data byte slave address s 1 aa a 8 11 1 8 command code 1 p 1 figure 16. smbus write byte protocol wr 7 data byte low slave address s 1 a a 8 11 1 command code 1 p 8 11 rd slave address s a a 7 1 1 1 figure 17. smbus read byte protocol ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 12 copyright 2011, taos inc. the lumenology company www.taosinc.com wr 7 data byte low slave address s 1 aa a 8 11 1 8 command code 1 p data byte high a 811 figure 18. smbus write word protocol wr 7 data byte low slave address s 1 a a 8 11 1 command code 1 p data byte high a 8 11 rd slave address s a a ... 7 1 811 1 figure 19. smbus read word protocol wr 8 data byte 1 slave address s 1 a a 8 11 1 command code p data byte n a 8 11 byte count = n a a ... 7 811 data byte 2 a 81 ... figure 20. smbus block write or i 2 c write protocols note: the i 2 c write protocol does not use the byte count packet, and the master will continue sending data bytes until the master initiates a stop condition. see the command register on page 13 for additional information regarding the block read/write protocol. wr 7 byte count = n slave address s 1 a a 8 11 1 command code p data byte n a 8 11 slave address a a ... 7 811 data byte 2 a 81 ... data byte 1 a 81 1 sr 1 rd 1 figure 21. smbus block read or i 2 c read (combined format) protocols note: the i 2 c read protocol does not use the byte count packet, and the master will continue receiving data bytes until the master initiates a stop condition. see the command register on page 13 for additional information regarding the block read/write protocol. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 13 the lumenology company copyright 2011, taos inc. www.taosinc.com register set the tcs3404/14 is controlled and monitored by 18 user registers and a command register accessed through the serial interface. these registers provide for a variety of control functions and can be read to determine results of the adc conversions. the register set is summarized in table 2. table 2. register set address register name register function ?? command specifies register address 00h control control of basic functions 01h timing integration time/gain control 02h interrupt interrupt control 03h int source interrupt source 04h id part number/ rev id 07h gain adc gain control 08h low_thresh_low_byte low byte of low interrupt threshold 09h low_thresh_high_byte high byte of low interrupt threshold 0ah high_thresh_low_byte low byte of high interrupt threshold 0bh high_thresh_high_byte high byte of high interrupt threshold 0fh ?? smbus block read (10h through 17h) 10h data1low low byte of adc green channel 11h data1high high byte of adc green channel 12h data2low low byte of adc red channel 13h data2high high byte of adc red channel 14h data3low low byte of adc blue channel 15h data3high high byte of adc blue channel 16h data4low low byte of adc clear channel 17h data4high high byte of adc clear channel the mechanics of accessing a specific register depends on the specific smb protocol used. refer to the section on smbus protocols on the previous pages. in general, the command register is written first to specify the specific control/status register for following read/write operations. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 14 copyright 2011, taos inc. the lumenology company www.taosinc.com command register the command register specifies the address of the target register for subsequent read and write operations. this register contains eight bits as described in table 3 and defaults to 00h at power on. table 3. command register 6 754 address 2 310 0 000 0 000 reset value: command cmd transaction field bits description cmd 7 select command register. must write as 1. transaction. selects type of transaction to follow in subsequent data transfer. field value transaction description 00 byte protocol smb read/write byte protocol transaction 6:5 01 word protocol smb read/write word protocol 10 block protocol smb read/write block protocol 11 interrupt clear clear any pending interrupt and is a write- once-to-clear field address 4:0 register address. this field selects the specific control or status register for following write and read com- mands according to table 2. notes: 1. an i 2 c block transaction will continue until the master sends a stop condition. see figure 18 and figure 19. unlike the i 2 c protocol, the tcs3404/14 smbus read/write protocol requires a byte count. all eight adc channel data registers (10h through 17h) can be read simultaneously in a single smbus transaction. this is the only 64-bit data block supported by the tcs3404 smbus protocol. the transaction field must be set to 10, and a read condition should be initiated with a command code of cfh. by using a command code of cfh during an smbus block read protocol, the tcs3404 device will automatically insert the appropriate byte count (byte count = 8) as illustrated in figure 18. a write condition should not be used in conjunction with the 0fh regi ster. 2. only the send byte protocol should be used when clearing interrupts. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 15 the lumenology company copyright 2011, taos inc. www.taosinc.com control register (00h) the control register contains two bits and is pri marily used to power the tcs3404/14 device up and down as shown in table 4. table 4. control register 6 754 power 2 310 0 000 0 000 reset value: control resv resv resv adc_valid resv 00h resv adc_en field bit description resv 7:6 reserved. write as 0. resv 5 reserved. write as 0. adc_valid 4 adc valid. this read-only field indicates that the adc channel has completed an integration cycle. resv 3:2 reserved. write as 0. adc_en 1 adc enable. this field enables the four adc channels to begin integration. writing a 1 activates the adc channels, and writing a 0 disables the adcs. power 0 power on. writing a 1 powers on the device, and writing a 0 turns it off. notes: 1. both adc_en and power must be asserted before the adc channels will operate correctly. 2. integ_mode and time/counter fields in the timing register (01h) should be written before adc_en is asserted. 3. if a value of 03h is written, the value returned during a read cycle will be 03h. this feature can be used to verify that the device is communicating properly. 4. during writes and reads, the power bit is overridden and the oscillator is enabled, independent of the state of power. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 16 copyright 2011, taos inc. the lumenology company www.taosinc.com timing register (01h) the timing register controls the synchronization and integration time of the adc channels. the timing register settings apply to all four adc channels. the timing register defaults to 00h at power on. table 5. timing register 6 754 param 2 310 0 000 0 000 reset value: timing sync_edge resv integ_mode 01h field bits description resv 7 reserved. write as 0. sync_edge 6 sync pin edge. if sync_edge is low, the falling edge of the sync pin is used to stop an integration cycle when integ_mode is 11. if sync_edge is high, the rising edge of the sync pin is used to stop an integration cycle when integ_mode is 11. selects preset integration time, manual integration (via serial bus), or external synchronization (sync in) modes. field value mode 00 in this mode, the integrator is free-running and one of the three internally-generated nominal integration times is selected for each conversion (see integration time table below). integ_mode 5:4 01 manually start/stop integration through serial bus using adc_en field in con- trol register. 10 synchronize exactly one internally-timed integration cycle as specified in the nominal integration time beginning 2.4 s after being initiated by the sync in pin. 11 integrate over specified number of pulses on sync in pin (see sync in pulse count table below). minimum width of sync pulse is 50 s. sync in must be low at least 3.6 s. uses single, multipurpose bitmapped field to select one of three predefined integration times or set the number of sync in pulses to count when the integ_mode accumulate mode (11) is selected. note: integ_mode and time/counter fields should be written before adc_en is asserted. field value nominal integration time 0000 12 ms 0001 100 ms 0010 400 ms param 3:0 field value sync in pulse count param 3 : 0 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 17 the lumenology company copyright 2011, taos inc. www.taosinc.com interrupt control register (02h) the interrupt register controls the extensive interrupt capabilities of the device. the open-drain interrupt pin is active low and requires a pullup resistor to v dd in order to pull high in the inactive state. using the interrupt source register (03h), the interrupt can be configured to trigger on any one of the four adc channels. the tcs3404/14 permits both smb-alert style interrupts as well as traditional level style interrupts. the interrupt register pr ovides control over when a meaningful interrupt will occur. the concept of a meaningful change can be defined by the user both in terms of light intensity and time, or persistence of that change in intensity. the value m ust cross the threshold (as configured in the threshold registers 08h through 0bh) and persist for some period of time as outlined in the table below. when a level interrupt is selected, an interrupt is generated whenever the last conversion results in a value outside of the programmed threshold window. the interrupt is active-low and remains asserted until cleared by writing an 11 in the transaction field in the command register. in smb-alert mode, the interrupt is similar to the traditional level style and the interrupt line is asserted low. to clear the interrupt, the host responds to the smb-alert by performing a modified receive byte operation, in which the alert response address (ara) is placed in the slave address field, and the tcs3404/14 that generated the interrupt responds by returning its own address in the seven most significant bits of the receive data byte. if more than one device connected on the bus has pulled the smbalert line low, the highest priority (lowest address) device will win control of the bus during the slave address transfer. if the device loses this arbitration, the interrupt will not be cleared. the alert response address is 0ch. when intr = 11, the interrupt is generated immediately following the smbus write operation. operation then behaves in an smb-alert mode, and the software set interrupt may be cleared by an smb-alert cycle. table 6. interrupt control register 6 7542 310 0 000 0 000 reset value: interrupt intr_stop resv intr resv 02h persist field bits description resv 7 reserved. write as 0. intr_stop 6 stop adc integration on interrupt. when high, adc integration will stop once an interrupt is asserted. to resume operation (1) de-assert adc_en using control register, (2) clear interrupt using command register, and (3) re-assert adc_en using control register. note : use this bit to isolate a particular condition when the sensor is continuously integrating. intr control select. this field determines mode of interrupt logic according to the table below: field value interrupt control 00 interrupt output disabled. intr 5:4 01 level interrupt. intr 5 : 4 10 smb-alert compliant. 11 sets an interrupt and functions as mode 10. note: value 11 may be used to test interrupt connectivity in a system or to assist in debugging interrupt service routine software. see application software section for further information. resv 3 reserved. write as 0. interrupt persistence. controls rate of interrupts to the host processor: field value timer description persist 2:0 000 every every adc cycle generates interrupt persist 2:0 001 single any value outside of threshold range. 010 0.1 sec consecutively out of range for 0.1 second 011 1 sec consecutively out of range for 1 second ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 18 copyright 2011, taos inc. the lumenology company www.taosinc.com interrupt source register (03h) the interrupt source register selects which adc channel value to use to generate an interrupt. only one of the four adc channels can be selected. table 7. interrupt source register 6 754 int source 2 310 0 000 0 000 reset value: int source resv resv resv resv resv 03h resv field bits description resv 7:2 reserved. write as 0. interrupt source. selects which adc channel to use to generate an interrupt: field value interrupt source int source 1:0 00 green channel int source 1:0 01 red channel 10 blue channel 11 clear channel note: the interrupt threshold register (08h?0bh) should be configured appropriately to correspond to the adc channel value that generates an interrupt. id register (04h) the id register provides the value for both the part number and silicon revision number for that part number. it is a read-only register, whose value never changes. table 8. id register 6 754 revno 2 310 ? ??? ? ??? reset value: id partno 04h field bits description partno 7:4 part number identification: field value 0000 = tcs3404 field value 0001 = tcs3413, TCS3414, tcs3415, and tcs3416 revno 3:0 revision number identification ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 19 the lumenology company copyright 2011, taos inc. www.taosinc.com gain register (07h) the gain register provides a common gain control adjustment for all four parallel adc output channels. two gain bits [5:4] in the gain register allow the relative gain to be adjusted from 1 to 64 in 4 increments. the advantage of the gain adjust is to extend the dynamic range of the light input up to a factor of 64 before analog or digital saturation occurs. if analog saturation has occurred, lowering the gain sensitivity will likely prevent analog saturation especially when the integration time is relatively short. for longer integration times, the 16-bit output could be in digital saturation (64k). if lowering the gain to 1 does not prevent digital saturation from occurring, the use of prescaler can be useful. the prescaler is 3 bits [2:0] in the gain register that divides down the output count (i.e. shifts the lsb of the count value to the right). the prescaler adjustment range is divide by 1 to 64 in multiples of 2. the most sensitive gain setting of the device would be when gain is set to 11b (64 ), and prescaler is set to 000b (divide by 1). the least sensitive part setting would be gain 00 (1 ) and prescaler 110 (divide by 64). if the part continues to be in digital saturation at the least sensitive setting, the integration time can be lowered (see timing register section). table 9. gain register 6 7542 310 0 000 0 000 reset value: gain resv gain resv 07h prescaler resv field bits description resv 7:6 reserved. write as 0. analog gain control. this field switches the common analog gain of the four adc channels. four gain modes are provided: field value gain gain 5:4 00 1 gain 5:4 01 4 10 16 11 64 resv 3 reserved. write as 0. prescaler. this field controls a 6-bit digital prescaler and divider. the prescaler reduces the sensitivity of each adc integrator as shown in the table below: field value prescaler mode 000 divide by 1. 001 divide by 2. prescaler 2:0 010 divide by 4. prescaler 2:0 011 divide by 8. 100 divide by 16. 101 divide by 32. 110 divide by 64. 111 not used. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 20 copyright 2011, taos inc. the lumenology company www.taosinc.com interrupt threshold register (08h ? 0bh) the interrupt threshold registers store the values to be used as the high and low trigger points for the comparison function for interrupt generation. the high and low bytes from each set of registers are combined to form a 16-bit threshold value. if the value generated by the interrupt source register (03h) converges below or equal to the low threshold specified, an interrupt is asserted on the interrupt pin. if the value generated by interrupt source register (03h) converges above the high threshold specified, an interrupt is asserted on the interrupt pin. registers low_thresh_low_byte and low_thresh_high_byte provide the low byte and high byte, respectively, of the lower interrupt threshold. registers high_thresh_low_byte and high_thresh_high_byte provide the low and high bytes, respectively, of the upper interrupt threshold. the interrupt threshold registers default to 00h on power up. table 10. interrupt threshold register register address bits description low_thresh_low_byte 08h 7:0 adc interrupt source lower byte of the low threshold. low_thresh_high_byte 09h 7:0 adc interrupt source upper byte of the low threshold. high_thresh_low_byte 0ah 7:0 adc interrupt source lower byte of the high threshold. high_thresh_high_byte 0bh 7:0 adc interrupt source upper byte of the high threshold. notes: 1. the interrupt source register (03h) selects which adc channel to generate an interrupt and should correspond to the thr eshold setting. both registers should be configured appropriately when setting up an interrupt service routine. 2. since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the smbus send byte protocol should not be used to write to these registers. any values transferred by the send byte protocol with the msb set woul d be interpreted as the command field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired. the write word protocol should be used to write byte-paired registers. for example, the low_thresh_low_byte and low_thresh_high_byte registers (as well as the high_thresh_low_byte and high_thresh_high_byte registers) can be written together to set the 16-bit adc value in a single transaction. adc channel data registers (10h ? 17h) the adc channel data are expressed as 16-bit values spread across four registers. the channel low and high provide the lower and upper bytes respectively for each adc channel data registers. each datalow and datahigh register is identified below as 1, 2, 3, or 4. all channel data registers are read-only and default to 00h on power up. table 11. adc channel data registers register address bits description green_low 10h 7:0 adc channel 1 lower byte green_high 11h 7:0 adc channel 1 upper byte red_low 12h 7:0 adc channel 2 lower byte red_high 13h 7:0 adc channel 2 upper byte blue_low 14h 7:0 adc channel 3 lower byte blue_high 15h 7:0 adc channel 3 upper byte clear_low 16h 7:0 adc channel 4 lower byte clear_high 17h 7:0 adc channel 4 upper byte the upper byte data registers can only be read following a read to the corresponding lower byte register. when the lower byte register is read the upper eight bits are strobed into a shadow register, which is read by a subsequent read to the upper byte. the upper register will therefore read the correct value even if additional adc integration cycles complete between the reading of the lower and upper registers. note: the smbus read word protocol can be used to read byte-paired registers. for example, the da ta1low and data1high registers (as well as the other three individual register pairs) may be read together to obtain the 16-bit adc value in a single transaction. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 21 the lumenology company copyright 2011, taos inc. www.taosinc.com application information: software basic operation after applying v dd , the device will initially be in the power?down state. to operate the device, issue a command to access the control register followed by the data value 03h to the control register to set adc_en and power to power up the device. at this point, all four adc channels will begin a conversion at the default integration time of 12 ms. after 12 ms, the conversion results will be available in adc channel data registers (10h through 17h). the following pseudo code illustrates a procedure for reading the tcs3404/14 device using word and byte transactions: // read adc channels using read word protocol ? recommended address = 0x39 command = 0x80 powerup = 0x03 //power up and enable adc //wait for integration conversion //address the ch1 lower data register and configure for read word command = 0xb0 //set command bit and word transaction //reads two bytes from sequential registers 10h and 11h //results are returned in datalow and datahigh variables readword (address, command, datalow, datahigh) channel1 = 256 * datahigh + datalow //address the ch2 lower data register and configure for read word command = 0xb2 //set command bit and word transaction //reads two bytes from sequential registers 12h and 13h //results are returned in datalow and datahigh variables readword (address, command, datalow, datahigh) channel2 = 256 * datahigh + datalow //shift datahigh to upper byte //address the ch3 lower data register and configure for read word command = 0xb4 //set command bit and word transaction //reads two bytes from sequential registers 14h and 15h //results are returned in datalow and datahigh variables readword (address, command, datalow, datahigh) channel3 = 256 * datahigh + datalow //address the ch4 lower data register and configure for read word command = 0xb8 //set command bit and word transaction //reads two bytes from sequential registers 16h and 17h //results are returned in datalow and datahigh variables readword (address, command, datalow, datahigh) channel4 = 256 * datahigh + datalow //shift datahigh to upper byte ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 22 copyright 2011, taos inc. the lumenology company www.taosinc.com // read adc channels using read byte protocol address = 0x39 //slave addr ? also 0x29 or 0x49 command = 0x90 //address the ch1 lower data register readbyte (address, command, datalow) //result returned in datalow command = 0x91 //address the ch1 upper data register readbyte (address, command, datahigh) //result returned in datahigh channel1 = 256 * datahigh + datalow //shift datahigh to upper byte command = 0x92 //address the ch2 lower data register readbyte (address, command, datalow) //result returned in datalow command = 0x93 //address the ch2 upper data register readbyte (address, command, datahigh) //result returned in datahigh channel2 = 256 * datahigh + datalow //shift datahigh to upper byte command = 0x94 //address the ch3 lower data register readbyte (address, command, datalow) //result returned in datalow command = 0x95 //address the ch3 upper data register readbyte (address, command, datahigh) //result returned in datahigh channel3 = 256 * datahigh + datalow //shift datahigh to upper byte command = 0x96 //address the ch4 lower data register readbyte (address, command, datalow) //result returned in datalow command = 0x97 //address the ch4 upper data register readbyte (address, command, datahigh) //result returned in datahigh channel4 = 256 * datahigh + datalow //shift datahigh to upper byte ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 23 the lumenology company copyright 2011, taos inc. www.taosinc.com application information: software configuring the timing register the command, timing, and control registers are initialized to default values on power up. setting these registers to the desired values would be part of a normal initialization or setup procedure. in addition, to maximize the performance of the device under various conditions, the integration time and gain may be changed often during operation. the following pseudo code illustrates a procedure for setting up the timing register for various options. // set up timing register //low gain (1x), integration time of 12ms (default value) address = 0x39 command = 0x81 //timing register data = 0x02 writebyte(address, command, data) //low gain (1x), integration time of 101ms command = 0x81 //timing register data = 0x01 writebyte(address, command, data) //low gain (1x), integration time of 12ms data = 0x00 writebyte(address, command, data) //high gain (16x), integration time of 101ms command = 0x81 //timing register data = 0x01 writebyte(address, command, data) command = 0x87 //gain control register data = 0x20 writebyte(address, command, data) //read data registers (see basic operation example) //perform manual integration of 50 us //set up for manual integration command = 0x80 data = 0x01 //disable adc_en writebyte(address, command, data) command = 0x81 data = 0x10 //set manual integration writebyte(address, command, data) command = 0x80 data = 0x03 //enable adc_en and begin integration writebyte(address, command, data) //integrate for 50ms sleep (50) //wait for 50ms //stop integrating command 0x80 data = 0x01 //disable adc_en and stop integration writebyte(address, command, data) //read data registers (see basic operation example) ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 24 copyright 2011, taos inc. the lumenology company www.taosinc.com application information: software synchronization there are two basic modes of operation for controlling synchronization: (1) internally timed, and (2) externally timed. internally-timed integration cycles can either be continuous back-to-back conversions or can be externally triggered as a single event using the sync pin. externally-timed integrations can be controlled by setting and clearing the adc enable in the control register using the serial interface, or by one or more pulses input to the sync pin. internally-timed integration cycle times are dependent on the param field value and the internal clock frequency. nominal integration times and respective scaling between integration times scale proportionally as shown in the param field in t able 5. see operating characteristics table notes for detailed information regarding how the scale values were obtained. if a particular integration time period is required that is not listed in the p aram integration time field value, then the manual timing control feature can be used to manually start and stop the integration time period by setting integ_mode=01b. manual integration is performed as follows: adc_en integration period time duration determined by length of time that adc_en = 1 interrupt ab figure 22. manual integration (integ_mode 01b) 1. disable adc_en (= 0) before initiating a manual integration cycle 2. clear and enable intr before each cycle 3. write 01b to integ_mode field 4. set adc_en (= 1) to start integration 5. clear adc_en ( = 0) to stop integration 6. read channel data ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 25 the lumenology company copyright 2011, taos inc. www.taosinc.com application information: software when the integ_mode field value is set to 10b, an externally-controlled synchronization input (sync) is used to trigger the start of an integration period. the integration period starts on the rising edge of the sync pulse, triggers a single, internally-timed integration cycle, and continues until the nominal integration time, as defined in the param field, is completed. sync in integration period time duration determined by param field (nominal integration time) interrupt ab note: adc_en must be toggled (i.e. from high to low and back to high again) before next integration cycle figure 23. one-shot integration (integ_mode 10b) falling edge 1. enable adc_en (= 1) 2. set param for desired integration cycle (12ms, 100ms, or 400ms) 3. set integ_mode to 10b 4. disable sync and clear intr 5. read channel data ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 26 copyright 2011, taos inc. the lumenology company www.taosinc.com application information: software when the integ_mode field value is set to 11b, the device integrates from the rising edge of the first pulse until the rising or falling edge of a subsequent pulse as specified by the sync_edge and param field values. see example timing diagrams below. adc_en must be toggled (i.e. from high to low and back to high again) before the next integration cycle. with this device feature, the sync in input pin can be used to synchronize the device with an external light source (e.g. led). sync in integration period interrupt ab notes: 1. rising edge of second sync in pulse required to terminate integration cycle 2. adc_en must be toggled (i.e. from high to low and back to high again) before next integration cycle figure 24. integrate over one pulse (sync_edge 1b, integ_mode 11b, param 0b) rising edge 1. enable adc_en (= 1) 2. set sync edge to 1 3. set param for sync pulse count of 1 4. set integ_mode to 11b 5. input two external sync pulses 6. disable sync and read channels ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 27 the lumenology company copyright 2011, taos inc. www.taosinc.com application information: software sync in interrupt ab integration period note: adc_en must be toggled (i.e. from high to low and back to high again) before next integration cycle figure 25. integrate over one pulse (sync_edge 0b, integ_mode 11b, param 0b) falling edge 1. enable adc_en (= 1) 2. set sync edge to 0 3. set param for sync pulse count of 1 4. set integ_mode to 11b 5. input external sync pulse 6. disable sync and read channels sync in integration period interrupt ab 1 n n+1 notes: 1. rising edge of third sync in pulse required to terminate integration cycle 2. adc_en must be toggled (i.e. from high to low and back to high again) before next integration cycle figure 26. integrate over two pulses (sync_edge 1b, integ_mode 11b, param xb) rising edge 1. enable adc_en (= 1) 2. set sync edge to 1 3. set param for desired sync pulse count 4. set integ_mode to 11b 5. input n+1 external sync pulses 6. disable sync and read channels ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 28 copyright 2011, taos inc. the lumenology company www.taosinc.com application information: software sync in integration period interrupt ab 1n note: adc_en must be toggled (i.e. from high to low and back to high again) before next integration cycle figure 27. integrate over two pulses (sync_edge 0b, integ_mode 11b, param xb) falling edge 1. enable adc_en (= 1) 2. set sync edge to 0 3. set param for desired sync pulse count 4. set integ_mode to 11b 5. input n external sync pulse(s) 6. disable sync and read channels ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 29 the lumenology company copyright 2011, taos inc. www.taosinc.com application information: software a synchronization input (sync in) is supported to precisely start/stop sensor integration and synchronize with the light source. the timing register (01h) provides two synchronization modes of operation. the first mode of operation synchronizes the sync in pin for one integration cycle as specified in the timing register (01h). when the rising edge of the signal is detected, the tcs3404/14 begins integration. the second mode accumulates a specified number of sync in pulses (see timing register) in which the minimum pulse width is 50 s. a pulse counter is used to count the rising and falling edges of the pulse(s) and precisely integrate the light level when the sync in pulse is high. the following pseudo code illustrates a procedure for reading the tcs3404/14 device using the synchronization feature: // synchronize one integration cycle // see ?basic operation? to power?on and start device // see ?configuring the timing register? to setup environment address = 0x39 //slave addr ? also 0x29 or 0x49 command = 0x81 //set command bit and address timing register data = 0x21 //sync one 100ms integration period //external sync in pulse initiates 100ms integration sleep (100) // see ?basic operation? to read data registers using byte or word protocol // synchronize n number of sync in pulses // see ?basic operation? to power?on and start device // see ?configuring the timing register? to setup environment address = 0x39 //slave addr ? also 0x29 or 0x49 command = 0x81 //set command bit and address timing register data = 0x30 //integrate one sync in pulse //external sync in pulse synchronizes integration // see ?basic operation? to read data registers using byte or word protocol ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 30 copyright 2011, taos inc. the lumenology company www.taosinc.com application information: software interrupts the interrupt feature of the tcs3404/14 device simplifies and improves system efficiency by eliminating the need to poll the sensor for a light intensity value. interrupt mode is determined by the intr field in the interrupt control register. the interrupt feature may be disabled by writing a field value of 00h to the interrupt control register (02h) so that polling can be performed. the versatility of the interrupt feature provides many options for interrupt configuration and usage. the primary purpose of the interrupt function is to signal a meaningful change in light intensity. however, it also be used as an end-of-conversion signal. the concept of a meaningful change can be defined by the user both in terms of light intensity and time, or persistence, of that change in intensity. the tcs3404/14 device implements two 16-bit-wide interrupt threshold registers that allow the user to define thresholds above and below a desired light level. an interrupt will then be generated when the value of a conversion exceeds either of these limits. for simplicity of programming, the threshold comparison uses the interrupt source register (03h) to select which adc channel (1 through 4) to generate the interrupt. this simplifies calculation of thresholds that are based on a percent of the current light level. for example, it is adequate to use only one channel (e.g. green channel) when calculating light intensity differences since, for a given light source, channel values are linearly proportional to each other and thus each value scales linearly with light intensity. to further control when an interrupt occurs, the tcs3404/14 device provides an interrupt persistence feature. this feature allows the user to specify the length in time of the number of consecutive adc channel values for which a light intensity exceeding either interrupt threshold must persist before actually generating an interrupt. this can be used to prevent transient changes in light intensity from generating an unwanted interrupt. see table 6 regarding the number of timer values provided. two different interrupt styles are available: level and smbus alert. the difference between these two interrupt styles is how they are cleared. both result in the interrupt line going active low and remaining low until the interrupt is cleared. a level style interrupt is cleared by setting the interrupt clear field in the the command register to 11b. the smbus alert style interrupt is cleared by an alert response as described in the interrupt control register section and smbus specification. to configure the interrupt as an end?of?conversion signal so that every adc integration cycle generates an interrupt, the interrupt persist field in the interrupt control register (02h) is set to 000b. either level or smbus alert style can be used. an interrupt will be generated upon completion of each conversion. the interrupt threshold registers are ignored. the following example illustra tes the configuration of a level interrupt: // set up end?of?conversion interrupt, level style address = 0x39 //slave address ? alternatively 0x29 or 0x49 command = 0x83 //interrupt source register data = 0x01 //select channel 2 writebyte(address, command, data) command = 0x82 //address interrupt register data = 0x10 //level style, every adc cycle writebyte(address, command, data) ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 31 the lumenology company copyright 2011, taos inc. www.taosinc.com application information: software the following example pseudo code illustrates the configuration of an smb-alert style interrupt when the light intensity changes 20% from the current value, and persists for 2.5 seconds: //assume interrupt source as channel 1 //read current light level address = 0x39 //slave address ? alternatively 0x29 or 0x49 command = 0xb0 //set command bit and smbus word read readword (address, command, datalow, datahigh) channel1 = (256 * datahigh) + datalow //calculate upper and lower thresholds t_upper = channel1 + (0.2 * channel1) t_lower = channel1 ? (0.2 * channel1) //write the lower threshold register command = 0xa8 //address lower threshold register, set word bit writeword (address, command, t_lower.lobyte, t_lower.hibyte) //write the upper threshold register command = 0xaa //address upper threshold register, set word bit writeword (address, command, t_upper.lobyte, t_upper.hibyte) //enable interrupt command = 0x82 //address interrupt register data = 0x24 //smbalert style, persist 2.5 seconds writebyte(address, command, data) in order to generate an interrupt on demand during system test or debug, a test mode (intr = 11) can be used. the following example illustrates how to generate an interrupt on demand: // generate an interrupt address = 0x39 //slave address alternately 0x29 or 0x49 command = 0x82 //address interrupt control register data = 0x30 //test interrupt writebyte(address, command, data) //interrupt line should now be low ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 32 copyright 2011, taos inc. the lumenology company www.taosinc.com application information: hardware power supply decoupling and application hardware circuit the power supply lines must be decoupled with a 0.1 f capacitor placed as close to the device package as possible (figure 28). the bypass capacitor should have low effective series resistance (esr) and low ef fective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents caused by internal logic switching. tcs3404/14 v bus v dd 0.1 f r p r p scl sda r pi int figure 28. bus pull-up resistors pull-up resistors (rp) maintain the sda and scl lines at a high level when the bus is free and ensure the signals are pulled up from a low to a high level within the required rise time. for a complete description of i 2 c maximum and minimum rp values, please review the nxp i 2 c design specification at http://www .i2c?bus.org/references/. a pull-up resistor (r pi ) is also required for the interrupt (int), which functions as a wired-and signal in a similar fashion to the scl and sda lines. a typical impedance value between 10 k and 100 k can be used. please note that while the figure above shows int being pulled up to v dd , the interrupt can optionally be pulled up to v bus . ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 33 the lumenology company copyright 2011, taos inc. www.taosinc.com application information: hardware pcb pad layout for cs package suggested pcb pad layout guidelines for the cs package are shown in figure 29. 6 0.30 0.95 0.61 0.61 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. figure 29. suggested cs package pcb layout pcb pad layout for fn package suggested pcb pad layout guidelines for the dual flat no-lead (fn) surface mount package are shown in figure 30. 0.40 3.50 0.40 1.25 2.30 0.95 1.25 0.95 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. figure 30. suggested fn package pcb layout ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 34 copyright 2011, taos inc. the lumenology company www.taosinc.com mechanical data package cs six-lead chipscale 950 nominal 350 10 1565 10 2095 463 30 610 nominal 438 30 top view bottom view end view lead free pb 6 300 30 pinout top view scl a1 sync a2 gnd a3 b1 sda b2 v dd b3 int photodiode array 1875 128 nominal c l of solder bumps and photodiode array area 6 160 30 405 20 685 45 c l of solder bumps c l of photodiode array area notes: a. all linear dimensions are in micrometers. dimension tolerance is 25 m unless otherwise noted. b. solder bumps are formed of sn (96.5%), ag (3%), and cu (0.5%). c. the layer above the photodiode is glass and epoxy with an index of refraction of 1.53. d. this drawing is subject to change without notice. figure 31. package cs ? six-lead chipscale packaging configuration ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 35 the lumenology company copyright 2011, taos inc. www.taosinc.com mechanical data package fn dual flat no-lead 203 8 6 gnd 5 vdd 4 int scl 1 sync 2 sda 3 t op view side view bottom view 300 50 950 3000 100 3000 100 pin 1 pin 1 end view 650 50 pin out top view 950 150 photodiode array 295 nominal lead free pb 350 10 1565 10 128 nominal c l of solder contacts c l of photodiode array area (note b) c l of solder contacts and photodiode array area (note b) notes: a. all linear dimensions are in micrometers. dimension tolerance is 20 m unless otherwise noted. b. the die is centered within the package within a tolerance of 3 mils. c. package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55 . d. contact finish is copper alloy a194 with pre-plated nipdau lead finish. e. this package contains no lead (pb). f. this drawing is subject to change without notice. figure 32. package fn ? dual flat no-lead packaging configuration ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 36 copyright 2011, taos inc. the lumenology company www.taosinc.com mechanical data top view detail a 2.12 0.05 a o 0.254 0.02 5 max 4.00 8.00 3.50 0.05 1.50 4.00 2.00 0.05 + 0.30 ? 0.10 1.75 b b aa detail b 2.30 0.05 b o 5 max 1.02 0.05 k o notes: a. all linear dimensions are in millimeters. dimension tolerance is 0.10 mm unless otherwise noted. b. the dimensions on this drawing are for illustrative purposes only. dimensions of an actual carrier may vary slightly. c. symbols on drawing a o , b o , and k o are defined in ansi eia standard 481?b 2001. d. each reel is 178 millimeters in diameter and contains 3500 parts. e. taos packaging tape and reel conform to the requirements of eia standard 481?b. f. in accordance with eia standard, device pin 1 is located next to the sprocket holes in the tape g. this drawing is subject to change without notice. figure 33. package cs carrier tape ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 37 the lumenology company copyright 2011, taos inc. www.taosinc.com mechanical data top view detail a 3.30 a o 0.254 0.02 10 max 4.00 8.00 3.50 0.05 1.50 4.00 2.00 0.05 + 0.30 ? 0.10 1.75 b b aa detail b 3.30 b o 12 max 0.80 k o notes: h. all linear dimensions are in millimeters. dimension tolerance is 0.10 mm unless otherwise noted. i. the dimensions on this drawing are for illustrative purposes only. dimensions of an actual carrier may vary slightly. j. symbols on drawing a o , b o , and k o are defined in ansi eia standard 481?b 2001. k. each reel is 178 millimeters in diameter and contains 3500 parts. l. taos packaging tape and reel conform to the requirements of eia standard 481?b. m. in accordance with eia standard, device pin 1 is located next to the sprocket holes in the tape n. this drawing is subject to change without notice. figure 34. package fn carrier tape ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 38 copyright 2011, taos inc. the lumenology company www.taosinc.com manufacturing information the cs and fn packages have been tested and has demonstrated an ability to be reflow soldered to a pcb substrate. the solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of pr oduct on a pcb. temperature is measured on top of component. the components should be limited to a maximum of three passes through this solder reflow profile. table 12. solder reflow profile parameter reference tcs3404/14 average temperature gradient in preheating 2.5 c/sec soak time t soak 2 to 3 minutes time above 217 c (t1) t 1 max 60 sec time above 230 c (t2) t 2 max 50 sec time above t peak ?10 c (t3) t 3 max 10 sec peak temperature in reflow t peak 260 c (?0 c/+5 c) temperature gradient in cooling max ?5 c/sec t 3 t 2 t 1 t soak t 3 t 2 t 1 t peak not to scale ? for reference only time (sec) temperature ( c) figure 35. solder reflow profile graph ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 39 the lumenology company copyright 2011, taos inc. www.taosinc.com manufacturing information moisture sensitivity optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package molding compound. to ensure the package molding compound contains the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping. devices are packed in a sealed aluminized envelope with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. cs package the cs package has been assigned a moisture sensitivity level of msl 2 and the devices should be stored under the following conditions: temperature range 5 c to 50 c relative humidity 60% maximum floor life 1 year out of bag at ambient < 30 c / 60% rh rebaking w ill be required if the aluminized envelope has been open for more than 1 year. if rebaking is required, it should be done at 50 c for 12 hours. fn package the fn package has been assigned a moisture sensitivity level of msl 3 and the devices should be stored under the following conditions: temperature range 5 c to 50 c relative humidity 60% maximum total time 12 months from the date code on the aluminized envelope ? if unopened opened time 168 hours or fewer rebaking w ill be required if the devices have been stored unopened for more than 12 months or if the aluminized envelope has been open for more than 168 hours. if rebaking is required, it should be done at 50 c for 12 hours. ams ag technical content still valid
tcs3404, TCS3414 digital color sensors taos137a ? april 2011 40 copyright 2011, taos inc. the lumenology company www.taosinc.com production data ? information in this document is current at publication date. products conform to specifications in accordance with the terms of texas advanced optoelectronic solutions, inc. standard warranty. production processing does not necessarily include testing of all parameters. lead-free (pb-free) and green statement pb-free (rohs) taos? terms lead-free or pb-free mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, taos pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br) taos defines green to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material). important information and disclaimer the information provided in this statement represents taos? knowledge and belief as of the date that it is provided. taos bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. taos has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. taos and taos suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. notice texas advanced optoelectronic solutions, inc. (t aos) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. customers are advised to contact taos to obtain the latest product information before placing orders or designing taos products into systems. taos assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. taos further makes no claim as to the suitability of its products for any particu lar purpose, nor does taos assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. texas advanced optoelectronic solutions, inc. products are not designed or intended for use in critical applications in which the failure or malfunction of the taos product may result in personal injury or death. use of t aos products in life support systems is expressly unauthorized and any such use by a customer is completely at the customer?s risk. lumenology, taos, the taos logo, and texas advanced optoelectronic solutions are registered trademarks of texas advanced optoelectronic solutions incorporated. ams ag technical content still valid

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